In this lesson, you’ll commence constructing your individual Minimal Actual-time Functioning Method (MiROS), where you will automate the context change.
In the very last lesson, you encountered the thought of a Actual-Time Working Process (RTOS), and you labored out a manual method of switching the context from just one thread to a further. In this lesson, you’ll commence constructing your own Negligible Actual-time Functioning Program (MiROS) , wherever you will automate the context switch.
Lesson 23 – RTOS: Automating the context swap
As I firmly believe that in learning by performing, I invite you to make the MiROS RTOS with me in the approach acknowledged as pair programming. We start out by adding a new group to the job with a header and resource documents. Then, we little by little fill in the facts, largely by copying, pasting, and modifying the snippets of code you experienced presently. By continuously getting two facet-by-side sights, we can more conveniently determine out the kernel API (Software Programming Interface) in a single look at though straight away seeking to use the API in the other. I hope you learn anything useful if you’ve under no circumstances labored like that.
The PendSV Exception
From the last lesson, you ought to bear in mind that the RTOS context switch “hijacks” the interrupt handling mechanism by now available in the CPU. Especially, by the conclude of an ISR (these as the SysTick_Handler in the video clip), you “trick” the CPU into returning to a unique thread than the a single preempted initially. For that, you’d have to include the context swap code to every ISR, which is inconvenient.
In ARM Cortex-M, ISRs can also nest (preempt each individual other), so only the return from the very last nested interrupt (back again to the thread amount) really should execute a context swap. The problem is that the order of ISR preemption changes dynamically at runtime, so you normally really do not know which one will be the very last.
An exquisite remedy employed in just about all RTOSs for ARM Cortex-M is to acquire gain of the same interrupt nesting system that established the issue in the 1st place. Especially, Cortex-M delivers the PendSV exception (Pend Assistance Contact) , which you can system to carry out the context swap and configure with the lowest interrupt priority (0xFF). When the RTOS detects the need to have to swap the context, it can pend the PendSV exception. The interrupt prioritization guarantees that PendSV will be the past ISR to run just just before returning to the thread level. In addition, the NVIC in ARM Cortex-M has a developed-in components optimization called “tail chaining,” which eliminates the overhead of exiting a person interrupt (e.g., SysTick) and getting into PendSV, so the context switch is executed with small overhead.
Coding the Context-Change in Assembly
The context swap in PendSV_Handler() are unable to be coded in common C due to the fact it needs to manipulate the Stack Pointer